1. Field of the Invention
Embodiments of the invention generally relate to an apparatus and method for performing multiple vapor deposition processes in-situ. More particularly, embodiments of the invention relate to an improved gas delivery apparatus and method for depositing films in-situ using both cyclical layer and chemical vapor deposition techniques.
2. Description of the Related Art
Sub-quarter micron multilevel metallization is one of the key technologies for the next generation of very large scale integration (VLSI). The multilevel interconnects that lie at the heart of this technology possess high aspect ratio features, including contacts, vias, lines, or other apertures. Reliable formation of these features is very important to the success of VLSI and to the continued effort to increase quality and circuit density on individual substrates. Therefore, there is a great amount of ongoing effort being directed to the formation of void-free features having high aspect ratios of 4:1 (height:width) or greater.
Copper has recently become a choice metal for filling VLSI features, such as sub-micron high aspect ratio, interconnect features, because copper and its alloys have lower resistivities than aluminum. However, copper and its alloys have a propensity to diffuse into surrounding materials such as silicon oxide, silicon, and other dielectric materials for example, causing an increase in the contact resistance of the circuit. Copper and its alloys also have a propensity to diffuse into surrounding elements such as transistor gates, capacitor dielectrics, transistor wells, transistor channels, electrical barrier regions, interconnects, among other known elements of integrated circuits. Barrier layers are, therefore, deposited prior to copper metallization to prevent or impede the diffusion of copper atoms.
A typical sequence for forming an interconnect includes depositing one or more non-conductive layers, etching at least one of the layer(s) to form one or more features therein, depositing a barrier layer in the feature(s) and depositing one or more conductive layers, such as copper, to fill the feature. The barrier layer typically includes a refractory metal such as tungsten, titanium, tantalum, and nitrides thereof. Of this group, tantalum nitride is one of the most desirable elements for use as a barrier layer because it has one of the lowest resistivities of the refractory metal nitrides and makes a good adhesion layer for copper metallization. A refractory metal nitride layer, such as tantalum nitride, is typically deposited using conventional deposition techniques, such as physical vapor deposition (PVD) and chemical vapor deposition (CVD).
Conventional deposition processes have difficulty forming interconnect structures because these processes have problems filling sub-micron structures where the aspect ratio exceeds 4:1, and particularly where the aspect ratio exceeds 10:1. Often, the barrier layer bridges the opening of a narrow feature, resulting in the formation of one or more voids or discontinuities within the feature. Since voids increase the resistance and reduce the electromigration resistance of the feature, features having voids make poor and unreliable electrical contacts.
Atomic layer deposition (ALD) is one deposition technique being explored to deposit materials, such as a barrier layer, over features having high aspect ratios. ALD involves the sequential introduction of separate pulses of a first reactant and a second reactant, resulting in a self-limiting absorption of monolayers of material on the substrate surface. The reactants are sequentially introduced until a desired thickness of the deposited material is deposited. A pulse of a purge gas and/or a pump evacuation between the pulses of the reactants serves to reduce the likelihood of gas phase reactions of the reactants due to excess amounts of the reactants remaining in the chamber.
Often within a typical fabrication sequence, a processed wafer is transferred between various processing chambers, consuming valuable processing time. Sometimes, the process wafer is subjected to a vacuum break between processing chambers and thus, the substrate is exposed to ambient conditions which, among other things, leads to oxidation of the substrate surface. Like voids, metal oxides increase the resistance of the interconnect and reduce the electromigration resistance of vias and small features. Metal oxides also become a source of particle problems and reduce the reliability of the overall circuit. Metal oxides may also interfere with subsequent deposition processes by creating voids that promote uneven distribution of a subsequent depositing layer.
There is a need, therefore, for a new method and apparatus for depositing multiple layers of material in-situ using multiple deposition techniques. Such a new method and apparatus would eliminate the need to transfer substrates between various processing chambers, and would reduce the likelihood of void formation.